An electronic part package that has a semiconductor chip and a resin part with which the semiconductor chip is covered has long been known (see Japanese Laid-open Patent Publication No. 2008-306071, for example). An example of such an electronic part package is described in the following.
FIG. 1 is a cross-sectional view exemplifying a conventional electronic part package. Referring to FIG. 1, an electronic part package 100 has a semiconductor chip 200 as an example of an electric part 200, a resin part 300, and a wiring structure 400.
The semiconductor chip 200 has a semiconductor chip main body 210 and electrode pads 220. The semiconductor chip main body 210 is configured so that a semiconductor integrated circuit (not illustrated) or the like is formed on a semiconductor substrate (not illustrated), which is a thin plate made of a semiconductor such as silicon.
The resin part 300 is provided in order to cover a surface 200a and surfaces 200b (side surfaces) of the semiconductor chip 200. An adhesive layer 510 is provided on a surface 200c, which is an opposite surface of the surface 200a of the semiconductor chip 200. Incidentally, the surface 200a may be referred to as a circuit forming surface; the surfaces 200b may be referred to as side surfaces; and the surface 200c may be referred to as a back surface.
The wiring structure 400 is formed by stacking a first wiring layer 410, a second wiring layer 420, a third wiring layer 430, a first insulating layer 440, and a second insulating layer 450.
Each of the wiring layers 410, 420, 430 is electrically connected with electrode pads 220 of the semiconductor chip 200 by way of vias 300x, 440x, 450x that go through the resin part 300 or the insulating layers 440, 450.
A solder resist layer 460 is formed on the second insulation layer 450 and covers the third wiring layer 430. The solder resist layer 460 has openings 460x, and parts of the third wiring layer 430 are exposed in the openings 460x. The third wiring layer 430 exposed in the openings 460x of the solder resist layer 460 functions as electrode pads connected with a motherboard or the like.
FIGS. 2 through 5 illustrate a manufacturing process of the electronic part package. The same or corresponding reference symbols are given to the same or corresponding parts or members, and repetitive explanation may be omitted. Sections (a) of FIGS. 2 and 3 are plan views, and sections (b) are cross-sectional views taken along A-A lines of the corresponding sections (a) of FIGS. 2 and 3. A conventional manufacturing method of the electric part package is explained with reference to FIGS. 2 and 3. Incidentally, the electrode pads 220 and the adhesive layer 510 are omitted in FIGS. 2 and 3.
First, the two or more semiconductor chips 200 are placed on a surface 500a of a supporting member 500 so that the surfaces 200c (back surfaces) oppose (or come in contact with) the surface 500a of the supporting member 500 in a process illustrated in FIG. 2. The adhesive layers 510 are formed in advance on the surfaces 200c of the semiconductor chips 200.
Next, the resin part 300 is formed by a compression molding method or the like on the surface 500a of the support member 500 thereby to cover the semiconductor chips 200 in a process illustrated in FIG. 3.
Next, the first wiring layer 410, the first insulating layer 440, the second wiring layer 420, the second insulating layer 450, and the solder resist layer 460 that has the third wiring layer 430 and the openings 460x are formed in this order on a surface 300a of the resin part 300, in a process illustrated in FIG. 4.
Next, the support member 500 is removed in a process illustrated in FIG. 5. With this, the surface 200c of the semiconductor chip 200, where the adhesive layer 510 is formed, is exposed from the surface 300b of the resin part 300.
Then, solder balls 470 (FIG. 1) are formed on the third wiring layer 43 exposed in the openings 460x of the solder resist layer 460. Next, the structure manufactured so far is cut along lines C illustrated in FIG. 5. As a result, the electric part package 100 illustrated in FIG. 1 is obtained.